1. Field of the Invention
The present invention relates to a semiconductor memory device and its operation method. The semiconductor memory device includes a memory cell having a data input node connected a write bit line and a data output node connected to a read bit line and also includes a sensor for sensing a difference in voltage between the write bit and read bit lines.
2. Description of the Related Art
The so-called gain cell is known as the memory cell having a data input node connected a write bit line and a data output node connected to a read bit line as described above. The gain cell is a memory cell, which has an amplification transistor for storing data by isolation signal BLIW are at the H level of 3.0 V whereas the read bit line RBL and the write bit line WBL are electrically connected to the RBL sense line RBL_SA and the WBL sense line WBL_SA respectively. Thus, the read bit line RBL and the RBL sense line RBL_SA are set at the same electric potential whereas the write bit line WBL and the WBL sense line WBL_SA are set at the same electric potential.
At that time, the Y switch signal YSW is at an L level as shown in FIG. 18I. This is because, since the Y-switch enable signal YSWE supplied to the nand circuit NAND14 shown in FIG. 14 is at an L level defined for an inactive state, the output of the nand circuit NAND14 is raised to an H level, pulling down the Y switch signal YSW to an L level. Thus, during the pre-charge period Tpc, the bit-line pair RBL-WBL and the sense-line pair RBL_SA-WBL_SA are electrically isolated from the global bit line pair GRBL-GWBL shown in FIG. 10, being put in a floating state.
When the RWL enable signal RWLE shown in FIG. 17B is raised to an H level, activating the read word line RWL shown in FIG. 18B, typically, a pulse of the power-supply voltage Vdd is applied. Thus, the select transistor ST shown in FIG. 1 is turned on. At that time, holding electric charge in a capacitive component added to the gate of the transistor, and allows the stored data to be read out from the capacitive component by converting the data into a change in the voltage appearing on the read bit line in accordance with whether the amplification transistor is at an on or off state at the read time dependently on the amount of the electric charge held in the capacitive component.
FIG. 1 is a diagram showing an equivalent circuit of a 3T (three transistors) gain cell, which is referred to hereafter simply as a memory cell MCa. The memory cell MCa shown in the figure has a write transistor WT and two read transistors, which are a select transistor ST and an amplification transistor AT.
One of the source and drain of the write transistor WT is connected to a write bit line WBL and the other is connected to a storage node SN. On the other hand, the gate of the write transistor WT is connected to a write word line WWL.
The source of the amplification transistor AT is connected to a CSL (common source line) serving as the ground and the drain of the amplification transistor AT is connected to the source of the select transistor ST. On the other hand, the gate of the amplification transistor AT is connected to the storage node SN.
The drain of the select transistor ST is connected to a read bit line RBL and the gate of the select transistor ST is connected to a read word line RWL.
FIG. 2 is a diagram showing a typical memory-cell system circuit.
As shown in FIG. 2, a plurality of memory cells MCa each shown in FIG. 1 are arranged in the column direction. The memory cells MCa share the read bit line RBL and the write bit line WRL, which form a pair of lines.
The pair of lines composing of the read bit line RBL and the write bit line WBL is connected to a pre-charge circuit 50 having two pre-charge transistors PTr and PTw, which are each a PMOS transistor. The drain of the pre-charge transistor PTr is connected to the read bit line RBL and the source of the pre-charge transistor PTr is connected to a supply line for supplying a voltage VRBL. On the other hand, the drain of the pre-charge transistor PTw is connected to the write bit line WBL and the source of the pre-charge transistor PTw is connected to a supply line for supplying a voltage VWBL. The two pre-charge transistors PTr and PTw are controlled by a common pre-charge enable line PRE.
The pair of lines composing of the read bit line RBL and the write bit line WBL is further connected to a cross couple latch sense amplifier, which is referred to hereafter simply as an SA (Sense Amplifier).
As shown in the figure, the sense amplifier SA includes two inverters, which are wired in cross connection, that is, the input of a specific one of the inverters is connected to the output of the other inverter and the output of the specific inverter is connected to the input of the other inverter. Each of the inverters includes a PMOS transistor 21 and an NMOS transistor 22.
A PMOS transistor 23 controlled by an SA enable inverted signal /SAEP, which is an active low signal, is connected to a junction point between a source common to the two PMOS transistors 21, 22 and a power-supply voltage line. On the other hand, an NMOS transistor 24 controlled by an SA enable signal SAEN, which is an active high signal, is connected to a junction point between a source common to the two NMOS transistors 22 and the ground line. The SA enable inverted signal /SAEP and the SA enable signal SAEN are each shared by other sensor amplifiers SA laid out in the row direction. It is to be noted, however, that the other sensor amplifiers SA are not shown in the figure.
The memory-cell control system circuit having the cross couple latch sense amplifier SA is described in documents such as Japanese Patent Laid-open No. 2001-291389.
A BL selector 6B is a circuit electrically disconnecting the read bit line RBL and the write bit line WBL, which are connected to the pre-charge circuit 50 and the sense amplifier SA, from other control circuits.
The BL selector 6B includes an NMOS switch 61r and an NMOS switch 61w. The NMOS switch 61r is connected between the read bit line RBL and a global read bit line GRBL. On the other hand, the NMOS switch 61w is connected between the write bit line WBL and a global write bit line GWBL.
FIGS. 3A to 3G are timing charts for operations to read out L data from the storage node SN. During the read operations, the write word line WWL is set at a low level indicating an inactive state all the time as shown in FIG. 3C.
As shown in FIG. 3A, an active-low pre-charge enable signal PRE is at an L level during a period of time ending at a time T0. Thus, during the period of time, the two pre-charge transistors PTr and PTw shown in FIG. 2 are both in an on state. As a result, the read bit line RBL is set (or pre-charged) at a voltage VRBL and the write bit line WBL is set (or pre-charged) at a voltage VWBL lower than the voltage VRBL. Typically, the voltage VRBL is the power-supply voltage Vdd (=1.8 V). On the other hand, the voltage VWBL is typically 1.4 V. At the time T0, the pre-charge enable signal PRE is set in an inactive state by raising the pre-charge enable signal PRE to an H level to set the read bit line RBL and the write bit line WBL in a floating state holding the pre-charge voltages as they are.
At a time T1, the read word line RWL is set at an H level by typically applying a pulse of the power-supply voltage Vdd as shown in FIG. 3B. Thus, the select transistor ST shown in FIG. 1 or 2 is turned on. Since the voltage appearing at the storage node SN is at an L level, however, the amplification transistor AT stays in the off state as it is. Thus, the read bit line RBL also remains at the power-supply voltage Vdd (=1.8 V) as it is.
At a time T2, the SA enable signal SAEN is raised to an H level in order to put the signal in an active state as shown in FIG. 3D. On the other hand, at the same time T2, the SA enable inverted signal /SAEP is pulled down to an L level also in order to put the signal in an active state as shown in FIG. 3E. Thus, the sense amplifier SA shown in FIG. 2 operates, amplifying a small electric-potential difference of about 0.4 V between the voltage appearing on the read bit line RBL and the voltage appearing on the write bit line WBL to a signal with an amplitude of 1.8 V. The state in which the voltage appearing on the read bit line RBL is higher than the voltage appearing on the write bit line WBL corresponds to the L data in the memory cell MCa.
Then, a Y-switch signal YSW shown in FIG. 3F is raised to an H level in order to turn on the NMOS switch 61r and the NMOS switch 61w, which are employed in the BL selector 6B as shown in FIG. 2, so as to supply the L data read out from the storage node SN to a control circuit provided at the following stage.
FIGS. 4A to 4G are timing charts for operations to read out H data from the storage node SN. Control of voltage levels in the operations to read out H data from the storage node SN as shown in FIGS. 4A to 4F is the same as that of the L-data read operations described above except that, during the operations to read out the H data from the storage node SN, the data is H data.
In the operations to read out the H data from the storage node SN, the data held in the storage node SN is set at a voltage level higher than a threshold voltage that allows the amplification transistor AT shown in FIG. 1 to enter an on state, and this voltage relation is sustained even during the read operations.
Thus, at a time T1, when the read word line RWL is put in an active state as shown in FIG. 4B in order to turn on the select transistor ST, a voltage is applied between the source and drain of the amplification transistor AT so that the amplification transistor AT is also turned on. Thus, a voltage appearing on the read bit line RBL is discharged to the common source line CSL by way of the select transistor ST and the amplification transistor AT, which have been turned on. As a result, a voltage reversion operation occurs as shown in FIG. 4G. In this voltage reversion operation, the voltage appearing on the read bit line RBL becomes lower than the voltage appearing on the write bit line WBL.
When the sense amplifier SA is put in an active state at a time T2 as shown in FIGS. 4D and 4E, the sense amplifier SA amplifies an electric-potential difference obtained after the voltage reversion operation mentioned above as the electric-potential difference between the voltage appearing on the read bit line RBL and the voltage appearing on the write bit line WBL to a signal with an amplitude of 1.8 V. The state in which the voltage appearing on the read bit line RBL is lower than the voltage appearing on the write bit line WBL corresponds to the H data in the memory cell MCa.
Then, the Y-switch signal YSW shown in FIG. 4F is raised to an H level activating the BL selector 6B shown in FIG. 2 so as to supply the H data read out from the storage node SN to a control circuit provided at the following stage.
FIGS. 5A to 5I are timing charts for operations to write L data into the storage node SN. On the other hand, FIGS. 6A to 6I are timing charts for operations to write H data into the storage node SN.
In either of the write operations with the timing charts thereof shown in FIGS. 5 and 6, the read operations described above need to be carried out before the write word line WWL is put in an active state at a time T4 in order to set a voltage for a refresh process on the write bit line WBL in advance for a reason described as follows.
FIG. 2 shows a configuration including only a column of memory cells included in an array of memory cells and a control circuit for the column of memory cells. In the following description, such a column is referred to as a column unit. In an actual semiconductor memory, however, a plurality of such column units having the same configuration are arranged in the row direction to form an array of memory cells. Memory cells on the same row in the array share a common write word line WWL and a common read word line RWL.
In a random access to such a semiconductor memory, for example, data is written into a predetermined number of memory cells on the same row. These memory cells on the same row form a write unit, which is typically referred to as a byte having a size of 8 bits. In this write operation, write data is set on the global write bit line GWBL in each column unit subjected to the write operation and the Y switch signal YSW is put in an active state in order to forcibly update the electric potential of the write bit line WBL to an electric potential determined by the write data.
As for a column unit not subjected to the write operation, a refresh operation is carried out in place of the write operation. That is to say, when data is read out from a memory cell, voltages output to the read bit line RBL and the write bit line WBL represents data obtained by logically inversion of the data stored in the memory cell as shown in FIGS. 3G and 4G. Thus, in this read-before-write process, the data stored in the memory cell is read out and represented by voltages asserted on the read bit line RBL and the write bit line WBL as voltages with a maximum difference of 1.8 V. For the column unit not subjected to the write operation, control is executed not to activate the Y switch signal YSW. In this way, a refresh process to write back the data represented by the voltages asserted on the read bit line RBL and the write bit line WBL can be carried out in the following activation of the write word line WWL.
As is obvious from the above description, in a semiconductor memory executing such control, a read process needs to be carried out prior to a write operation in order to set a voltage for a refresh process on the write bit line WBL in advance. In the following description, this read process is also referred to as a read-before-write process.
Prior to a time T3 shown in FIGS. 5 and 6, the read operations explained earlier by referring to FIGS. 3 and 4 are carried out as read-before-write processes. The explanation of the read operations explained earlier by referring to FIGS. 3 and 4 is not repeated in the following description in order to avoid duplication. In the following description, the read process carried out prior to the time T3 is also referred to as a read-before-write process as described above and the write operation carried out after the time T3 is also referred to as a write process.
Since the relation of voltages in the L-data write operation shown in FIG. 5 is opposite to the relation of voltages in the H-data write operation shown in FIG. 6, however, the voltages set on the global read bit line GRBL and the global write bit line GWBL in the L-data write operation shown in FIG. 5 may be voltages obtained by inversion of the voltages set on the global read bit line GRBL and the global write bit line GWBL respectively in the H-data write operation shown in FIG. 6.
To put it concretely, a high-level voltage of 1.8 V is set on the global read bit line GRBL in the L-data write operation as shown in FIG. 5H whereas a low-level voltage of 0 V is set on the global write bit line GWBL in the L-data write operation as shown in FIG. 5I.
On the other hand, the low-level voltage of 0 V is set on the global read bit line GRBL in the H-data write operation as shown in FIG. 6H whereas the high-level voltage of 1.8 V is set on the global write bit line GWBL in the H-data write operation as shown in FIG. 6I.
After the read-before-write process is completed, the Y switch signal YSW shown in FIG. 2 is put in an active state at the time T3. As soon as the Y switch signal YSW is put in an active state, the relation of voltages set on the read bit line RBL and the write bit line WBL of the column unit including memory cells subjected to the L-data write operation shown in FIG. 5 or the relation of voltages set on the read bit line RBL and the write bit line WBL of the column unit including memory cells subjected to the H-data write operation shown in FIG. 6 is inverted. In other words, such voltages are set on the global read bit line GRBL and the global write bit line GWBL in the read-before-write process in advance that a post-read write process carried out on each memory cell subjected to the write operation is a process to write data obtained by inversion of data obtained as a result of the read-before-write process to read out data currently stored in each memory cell.
As for a column unit including memory cells not subjected to the write operation, the Y switch signal YSW is not raised to an H level of the active state. Thus, the relation of voltages set on the read bit line RBL and the write bit line WBL of the column unit including these memory cells is sustained even after the time T3 in the same state as the relation right before the time T3. It is to be noted that timing charts for a column unit including memory cells not subjected to the write operation are not shown in any figure.
Then, at the time T4, the write word line WWL is raised to an H level as shown in FIG. 5C or 6C. In this state, the write transistor WT shown in FIG. 1 is turned on, allowing the write data forcibly set on the write bit line WBL into the storage node SN.
At that time, in the column unit not selected by the Y switch signal YSW, data obtained as a result of amplifying a voltage originally appearing on the storage node SN is read out and output to the write bit line WBL as described earlier. Thus, by activating the write word line WWL, the data appearing on the write bit line WBL is again written into the storage node SN of the unselected memory cell in an operation referred to as the refresh process cited before.
After the write operation, the voltage appearing on the write word line WWL is pulled down to an L level of 0 V as shown in FIG. 5 or 6 in order to turn off the write transistor WT. At that time, the voltage appearing on the read word line RWL is sustained at 0 V and the off state of the select transistor ST is maintained as it is till the next read operation. In this standby state, the storage node SN is put in a floating state, holding the electric charge stored therein.
The electric charge held in the storage node SN is stored mainly in a capacitance between a diffusion layer on the source side of the write transistor WT, the substrate and the gate of the write transistor WT and the capacitance of the MOS gate of the amplification transistor AT. Thus, the voltage appearing on the storage node SN decreases with the lapse of time due to, among others, a diffusion-layer junction leak in the write transistor WT and a gate leak in the amplification transistor AT. Since the voltage appearing on the storage node SN decreases with the lapse of time, it is necessary to carry out a refresh operation every time a predetermined period of time lapses since a write operation. In the configuration described above, a refresh operation can be carried out on a specific memory cell in an operation to write data into another memory cell connected on the same row as the specific memory cell.